The latest developments in mobile computing technology have enabled intensive applications on the modern Smartphones. However, such applications are still constrained by limitations in processing potentials, storage capacity and battery lifetime of the Smart Mobile Devices (SMDs). Therefore, Mobile Cloud Computing (MCC) leverages the application processing services of computational clouds for mitigating resources limitations in SMDs. Currently, a number of computational offloading frameworks are proposed for MCC wherein the intensive components of the application are outsourced to computational clouds. Nevertheless, such frameworks focus on runtime partitioning of the application for computational offloading, which is time consuming and resources intensive. The resource constraint nature of SMDs require lightweight procedures for leveraging computational clouds. Therefore, this paper presents a lightweight framework which focuses on minimizing additional resources utilization in computational offloading for MCC. The framework employs features of centralized monitoring, high availability and on demand access services of computational clouds for computational offloading. As a result, the turnaround time and execution cost of the application are reduced. The framework is evaluated by testing prototype application in the real MCC environment. The lightweight nature of the proposed framework is validated by employing computational offloading for the proposed framework and the latest existing frameworks. Analysis shows that by employing the proposed framework for computational offloading, the size of data transmission is reduced by 91%, energy consumption cost is minimized by 81% and turnaround time of the application is decreased by 83.5% as compared to the existing offloading frameworks. Hence, the proposed framework minimizes additional resources utilization and therefore offers lightweight solution for computational offloading in MCC.
This journal presents an ultra-low-voltage current bleeding mixer with high LO-RF port-to-port isolation, implemented on 0.13 μm standard CMOS technology for ZigBee application. The architecture compliments a modified current bleeding topology, consisting of NMOS-based current bleeding transistor, PMOS-based switching stage, and integrated inductors achieving low-voltage operation and high LO-RF isolation. The mixer exhibits a conversion gain of 7.5 dB at the radio frequency (RF) of 2.4 GHz, an input third-order intercept point (IIP3) of 1 dBm, and a LO-RF isolation measured to 60 dB. The DC power consumption is 572 µW at supply voltage of 0.45 V, while consuming a chip area of 0.97 × 0.88 mm(2).
In recent times, the size of biological databases has increased significantly, with the continuous growth in the number of users and rate of queries; such that some databases have reached the terabyte size. There is therefore, the increasing need to access databases at the fastest rates possible. In this paper, the decision tree indexing model (PDTIM) was parallelised, using a hybrid of distributed and shared memory on resident database; with horizontal and vertical growth through Message Passing Interface (MPI) and POSIX Thread (PThread), to accelerate the index building time. The PDTIM was implemented using 1, 2, 4 and 5 processors on 1, 2, 3 and 4 threads respectively. The results show that the hybrid technique improved the speedup, compared to a sequential version. It could be concluded from results that the proposed PDTIM is appropriate for large data sets, in terms of index building time.
Technology scaling relies on reduced nodal capacitances and lower voltages in order to improve performance and power consumption, resulting in significant increase in layout density, thus making these submicron technologies more susceptible to soft errors. Previous analysis indicates a significant improvement in SEU tolerance of the driver when the bias current is injected into the circuit but results in increase of power dissipation. Subsequently, other alternatives are considered. The impact of transistor sizes and temperature on SEU tolerance is tested. Results indicate no significant changes in Q(crit) when the effective transistor length is increased by 10%, but there is an improvement when high temperature and high bias currents are applied. However, this is due to other process parameters that are temperature dependent, which contribute to the sharp increase in Q(crit). It is found that, with temperature, there is no clear factor that can justify the direct impact of temperature on the SEU tolerance. Thus, in order to improve the SEU tolerance, high bias currents are still considered to be the most effective method in improving the SEU sensitivity. However, good trade-off is required for the low-swing driver in order to meet the reliability target with minimal power overhead.