Negative bias temperature instability (NBTI) is a common phenomenon in a p-channel MOSFET device
under a negative gate-to-source voltage at a high stress temperature. This paper presents the NBTI
characterisation based on different analysis methods and stress conditions on p-MOSFET devices. The
atomic hydrogen concentration is probed at interface, Poly-Si and channel of p-MOSFET under study
using SILVACO TCAD tool. In addition, the behaviour of the permanent and recoverable component
was investigated based on AC stress at different stress conditions using Modelling Interface Generation
(MIG) tool. The results show that increases in temperature, negative voltage stress gate and decreases
in frequency increase the threshold voltage shift, thus enhancing NBTI degradation.
Negative bias temperature instability (NBTI) is the most concern issue CMOS devices with the scaling
down of the CMOS technologies. NBTI effect contributes to P-MOSFET device degradation which later
reduce the performance and reliability of CMOS circuits. This paper presents a reliability simulation study
based on R-D model on CMOS inverter circuit. HSPICE MOSRA model together with the Predictive
Technology Model (PTM) was used as to incorporate the NBTI model in the circuit reliability simulation
study for different technology nodes. PTM of High Performance (HP) models of 16nm, 22nm, 32nm
and 45nm were used in this simulation study. The atomic hydrogen based model was integrated in the
simulation. The results show that in a CMOS inverter circuit, the threshold voltage shift of p-MOSFET
under NBTI stressing increased as the year progressed.. The threshold voltage shift was observed to
increase up to 45.1% after 10 years of operation. The time exponent, n ~ 0.232 of the threshold voltage
shift observed indicates that the defect mechanism contributed to the degradation is atomic hydrogen.
The propagation delay increased to 19.5% over a 10-year period. s up to 19.5% from the zero year
of operation until 10 years of the operation. In addition, the time propagation delay increased as year
increased when the technology nodes smaller. The finding is important for understanding reliability
issues related to advanced technology nodes in CMOS circuits study.