One of the most important goals in bioinformatics is the ability to predict tertiary structure of a protein from its amino acid sequence. In this paper, new feature groups based on the physical and physicochemical properties of amino acids (size of the amino acids' side chains, predicted secondary structure based on normalized frequency of β-Strands, Turns, and Reverse Turns) are proposed to tackle this task. The proposed features are extracted using a modified feature extraction method adapted from Dubchak et al. To study the effectiveness of the proposed features and the modified feature extraction method, AdaBoost.M1, Multi Layer Perceptron (MLP), and Support Vector Machine (SVM) that have been commonly and successfully applied to the protein folding problem are employed. Our experimental results show that the new feature groups altogether with the modified feature extraction method are capable of enhancing the protein fold prediction accuracy better than the previous works found in the literature.
This paper examines the impact of two important geometrical parameters, namely the thickness and source/drain extensions on the performance of low doped p-type double lateral gate junctionless transistors (DGJLTs). The three dimensional Technology Computer-Aided Design simulation is implemented to calculate the characteristics of the devices with different thickness and source/drain extension and based on that, the parameters such as threshold voltage, transconductance and resistance in saturation region are analyzed. In addition, simulation results provide a physical explanation for the variation of device characteristics given by the variation of geometric parameters, mainly based on investigation of the electric field components and the carries density variation. It is shown that, the variation of the carrier density is the main factor which affects the characteristics of the device when the device's thickness is varied. However, the electric field is mainly responsible for variation of the characteristics when the source/drain extension is changed.
A multi-gate n-type In₀.₅₃Ga₀.₄₇As MOSFET is fabricated using gate-first self-aligned method and air-bridge technology. The devices with different gate lengths were fabricated with the Al2O3 oxide layer with the thickness of 8 nm. In this letter, impact of gate length variation on device parameter such as threshold voltage, high and low voltage transconductance, subthreshold swing and off current are investigated at room temperature. Scaling the gate length revealed good enhancement in all investigated parameters but the negative shift in threshold voltage was observed for shorter gate lengths. The high drain current of 1.13 A/mm and maximum extrinsic transconductance of 678 mS/mm with the field effect mobility of 364 cm(2)/Vs are achieved for the gate length and width of 0.2 µm and 30 µm, respectively. The source/drain overlap length for the device is approximately extracted about 51 nm with the leakage current in order of 10(-8) A. The results of RF measurement for cut-off and maximum oscillation frequency for devices with different gate lengths are compared.
Polyimide/SiO(2) composite films were prepared from tetraethoxysilane (TEOS) and poly(amic acid) (PAA) based on aromatic diamine (4-aminophenyl sulfone) (4-APS) and aromatic dianhydride (3,3,4,4-benzophenonetetracarboxylic dianhydride) (BTDA) via a sol-gel process in N-methyl-2-pyrrolidinone (NMP). The prepared polyimide/SiO(2) composite films were characterized using X-ray diffraction (XRD), Fourier transform infrared spectroscopy (FTIR), scanning electron microscope (SEM) and thermogravimetric analysis (TGA). The FTIR results confirmed the synthesis of polyimide (4-APS/BTDA) and the formation of SiO(2) particles in the polyimide matrix. Meanwhile, the SEM images showed that the SiO(2) particles were well dispersed in the polyimide matrix. Thermal stability and kinetic parameters of the degradation processes for the prepared polyimide/SiO(2) composite films were investigated using TGA in N(2) atmosphere. The activation energy of the solid-state process was calculated using Flynn-Wall-Ozawa's method without the knowledge of the reaction mechanism. The results indicated that thermal stability and the values of the calculated activation energies increased with the increase of the TEOS loading and the activation energy also varied with the percentage of weight loss for all compositions.
The junctionless nanowire transistor is a promising alternative for a new generation of nanotransistors. In this letter the atomic force microscopy nanolithography with two wet etching processes was implemented to fabricate simple structures as double gate and single gate junctionless silicon nanowire transistor on low doped p-type silicon-on-insulator wafer. The etching process was developed and optimized in the present work compared to our previous works. The output, transfer characteristics and drain conductance of both structures were compared. The trend for both devices found to be the same but differences in subthreshold swing, 'on/off' ratio, and threshold voltage were observed. The devices are 'on' state when performing as the pinch off devices. The positive gate voltage shows pinch off effect, while the negative gate voltage was unable to make a significant effect on drain current. The charge transmission in devices is also investigated in simple model according to a junctionless transistor principal.
A double-lateral-gate p-type junctionless transistor is fabricated on a low-doped (10(15)) silicon-on-insulator wafer by a lithography technique based on scanning probe microscopy and two steps of wet chemical etching. The experimental transfer characteristics are obtained and compared with the numerical characteristics of the device. The simulation results are used to investigate the pinch-off mechanism, from the flat band to the off state. The study is based on the variation of the carrier density and the electric-field components. The device is a pinch-off transistor, which is normally in the on state and is driven into the off state by the application of a positive gate voltage. We demonstrate that the depletion starts from the bottom corner of the channel facing the gates and expands toward the center and top of the channel. Redistribution of the carriers due to the electric field emanating from the gates creates an electric field perpendicular to the current, toward the bottom of the channel, which provides the electrostatic squeezing of the current.
In this letter, we investigate the fabrication of Silicon nanostructure patterned on lightly doped (10(15) cm(-3)) p-type silicon-on-insulator by atomic force microscope nanolithography technique. The local anodic oxidation followed by two wet etching steps, potassium hydroxide etching for silicon removal and hydrofluoric etching for oxide removal, are implemented to reach the structures. The impact of contributing parameters in oxidation such as tip materials, applying voltage on the tip, relative humidity and exposure time are studied. The effect of the etchant concentration (10% to 30% wt) of potassium hydroxide and its mixture with isopropyl alcohol (10%vol. IPA ) at different temperatures on silicon surface are expressed. For different KOH concentrations, the effect of etching with the IPA admixture and the effect of the immersing time in the etching process on the structure are investigated. The etching processes are accurately optimized by 30%wt. KOH +10%vol. IPA in appropriate time, temperature, and humidity.