This paper presents the effects of calcination time and sintering temperature on the properties of CaCu(3)Ti(4)O(12). Electroceramic material of CaCu(3)Ti(4)O(12) was prepared using a modified mechanical alloying technique that covers several processes, which are preparation of raw material, mixing and ball milling for 5 hours, calcination, pellet forming and, sintering. The objective of this modified technique is to enable the calcination and sintering processes to be carried out at a shorter time and lower temperature. The x-ray diffraction (XRD) analysis result shows that a single-phase of CaCu(3)Ti(4)O(12) was completely formed by calcination at 750 degrees C for 12 hours. Meanwhile, the grain size of a sample sintered at 1050 degrees C for 24 hours is extremely large, in the range of 20-50 mum obtained from field emission scanning electron microscopy (FESEM) images. The dielectric constant value of 14,635 was obtained at 10 kHz by impedance (LCR) meter in the sintered sample at 1050 degrees C. However, the dielectric constant value of samples sintered at 900 and 950 degrees C is quite low, in the range of 52-119.
Silicon nanowires (SiNWs) were fabricated by the electroless etching of an n-type Si (100) wafer in HF/AgNO3. Vertically aligned and high-density SiNWs are formed on the Si substrates. Various shapes of SiNWs are observed, including round, rectangular, and triangular. The recorded maximum reflectance of the SiNWs is approximately 19.2%, which is much lower than that of the Si substrate (65.1%). The minimum reflectance of the SiNWs is approximately 3.5% in the near UV region and 9.8% in the visible to near IR regions. The calculated band gap energy of the SiNWs is found to be slightly higher than that of the Si substrate. The I-V characteristics of a freestanding SiNW show a linear ohmic behavior for a forward bias up to 2.0 V. The average resistivity of a SiNW is approximately 33.94 Ω cm.
The junctionless nanowire transistor is a promising alternative for a new generation of nanotransistors. In this letter the atomic force microscopy nanolithography with two wet etching processes was implemented to fabricate simple structures as double gate and single gate junctionless silicon nanowire transistor on low doped p-type silicon-on-insulator wafer. The etching process was developed and optimized in the present work compared to our previous works. The output, transfer characteristics and drain conductance of both structures were compared. The trend for both devices found to be the same but differences in subthreshold swing, 'on/off' ratio, and threshold voltage were observed. The devices are 'on' state when performing as the pinch off devices. The positive gate voltage shows pinch off effect, while the negative gate voltage was unable to make a significant effect on drain current. The charge transmission in devices is also investigated in simple model according to a junctionless transistor principal.
A double-lateral-gate p-type junctionless transistor is fabricated on a low-doped (10(15)) silicon-on-insulator wafer by a lithography technique based on scanning probe microscopy and two steps of wet chemical etching. The experimental transfer characteristics are obtained and compared with the numerical characteristics of the device. The simulation results are used to investigate the pinch-off mechanism, from the flat band to the off state. The study is based on the variation of the carrier density and the electric-field components. The device is a pinch-off transistor, which is normally in the on state and is driven into the off state by the application of a positive gate voltage. We demonstrate that the depletion starts from the bottom corner of the channel facing the gates and expands toward the center and top of the channel. Redistribution of the carriers due to the electric field emanating from the gates creates an electric field perpendicular to the current, toward the bottom of the channel, which provides the electrostatic squeezing of the current.
In this letter, we investigate the fabrication of Silicon nanostructure patterned on lightly doped (10(15) cm(-3)) p-type silicon-on-insulator by atomic force microscope nanolithography technique. The local anodic oxidation followed by two wet etching steps, potassium hydroxide etching for silicon removal and hydrofluoric etching for oxide removal, are implemented to reach the structures. The impact of contributing parameters in oxidation such as tip materials, applying voltage on the tip, relative humidity and exposure time are studied. The effect of the etchant concentration (10% to 30% wt) of potassium hydroxide and its mixture with isopropyl alcohol (10%vol. IPA ) at different temperatures on silicon surface are expressed. For different KOH concentrations, the effect of etching with the IPA admixture and the effect of the immersing time in the etching process on the structure are investigated. The etching processes are accurately optimized by 30%wt. KOH +10%vol. IPA in appropriate time, temperature, and humidity.