This paper describes how to employ distributed clock gating to achieve an overall low power design of a programmable waveform generator intended for a neural stimulator. The power efficiency is enabled using global timing control combined with local amplitude distribution over a bus to the local stimulator frontends. This allows the combination of local and global clock gating for complete sub-blocks of the design. A counter and a shifter employed at the local digital stimulator reduce the design complexity for the waveform generation and thus the overall power consumptions. The average power results indicate that 63% power can be saved for the global stimulator control unit and 89-96% power can be saved for the local digital stimulator by using the proposed approach. The circuit has been implemented and successfully tested in a 0.35 µm AMS HVCMOS technology.
Functional electrical stimulation (FES) device has been widely used by spinal cord injury (SCI) patients in their rehab exercises to restore motor function to their paralysed muscles. The major challenge of muscle contraction induced by FES is early muscle fatigue due to the open-loop stimulation strategy. To reduce the early muscle fatigue phenomenon, a closed-loop FES system is proposed to track the angle of the limb's movement and provide an accurate amount of charge according to the desired reference angle. Among the existing feedback controllers, fuzzy logic controller (FLC) has been found to exhibit good control performance in handling complex non-linear systems without developing any complex mathematical model. Recently, there has been considerable interest in the implementation of FLC in hardware embedded systems. Therefore, in this paper, a digital fuzzy feedback controller (FFC) embedded in a field-programmable gate array (FPGA) board was proposed. The digital FFC mainly consists of an analog-to-digital converter (ADC) Data Acquisition and FLC sub-modules. The FFC was designed to monitor and control the progress of knee extension movement by regulating the stimulus pulse width duration to meet the target angle. The knee is expected to extend to a maximum reference angle setting (70°, 40° or 30°) from its normal position of 0° once the stimulus charge is applied to the muscle by the FES device. Initially, the FLC was modelled using MATLAB Simulink. Then, the FLC was hardcoded into digital logic using hardware description language (HDL) Verilog codes. Thereafter, the performance of the digital FLC was tested with a knee extension model using the HDL co-simulation technique in MATLAB Simulink. Finally, for real-time verification, the designed digital FFC was downloaded to the Intel FPGA (DE2-115) board. The digital FFC utilized only 4% of the total FPGA (Cyclone IV E) logic elements (LEs) and required 238 µs to regulate stimulus pulse width data, including 3 µs for the FLC computation. The high processing speed of the digital FFC enables the stimulus pulse width duration to be updated every stimulation cycle. Furthermore, the implemented digital FFC has demonstrated good control performance in accurately controlling the stimulus pulse width duration to reach the desired reference angle with very small overshoot (1.4°) and steady-state error (0.4°). These promising results are very useful for a real-world closed-loop FES application.